vhdl
美英
- n.极高密度脂蛋白
- 网络硬件描述语言；高速集成电路硬件描述语言(VHSIC hardware description language)；极高密度脂蛋白(very high density lipoprotein)
vhdlvhdl
硬件描述语言
计算机硬件描述语言(VHDL)与编程语言（C语言）的区别及关系，满意答案 好评率：100% 10 [ 标签：计算机硬件, vhdl, 编程 …
高速集成电路硬件描述语言(VHSIC hardware description language)
VHDL(VHSIC Hardware Description Language)是一个详细且庞大的硬件描述语言。它在20世纪80年代后期由美国国防部开发…
极高密度脂蛋白(very high density lipoprotein)
另外还有极高密度脂蛋白（VHDL），密度范围为1.210～1.250g/ml。表2-1 人血浆脂蛋白的种类及一般特性 乳糜微粒 VLDL LD…
硬件设计者辅助软件
软件列表 ... （MEMS 系统设计、制造和模拟软件） (VHDL 编译器和模拟器,硬件设计者辅助软件) (GIS 空间数据服务器) ...
硬体描述语言(Verilog Hardware Description Language)
接著使用硬体描述语言(VHDL)将调变指数及相位角控制电路合成於FPGA中。最后将已开发晶片应用在不断电系统之中，并由 …
数字逻辑设计
·数字逻辑设计(VHDL)基础(英文版)(时代教育·国外高校优秀教材精选)(Fundamentals of Digital Logic with VHDL Design) ￥63 …
1
No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board.
最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。
2
Extensive testing was required to both ensure that the VHDL models behaved properly and to ensure that the FPGA did not damage the NES.
需要做更多的测试，确保VHDL模块的行为正确，并确保FPGA没有损坏任天堂系统。
3
By modeling, designing in VHDL, and down-loading the designed programs into a FPGA hardware.
系统基带电路通过VHDL建模与设计，并在高速FPGA芯片中实现。
4
NC VHDL divider based on the design, the whole process simple, fast, easy to modify, strong portability.
基于VHDL的数控分频器设计，整个过程简单、快捷，极易修改，可移植性强。
5
The ISE user interface allows you to add entities either in a schematic view or as HDL objects (either Verilog or VHDL).
ISE用户界面允许您在示意图视图添加实体或将其作为HDL对象（Verilog或VHDL）添加。
6
Once I determined what I needed, I began researching the NES and VHDL implementations of the CPU it uses.
在我定下自己的需要后，我开始研究如果用VHDL做出任天堂游戏机的CPU。
7
Chapter three introduces the VHDL- a sort of-hardware design describe language.
第三章介绍了系统实现的硬件描述语言VHDL。
8
On the side of software, the design method of control program completed with language VHDL is provided.
软件方面给出了用VHDL语言编写控制程序的设计思路；
9
As a common kind of language for description of hardware, VHDL was once widely applied in circuit design.
VHDL作为一种通用的硬件描述语言，在电路设计中被广泛使用。
10
This thesis using FPGA devices and VHDL hardware description language to completed the design and realization of USB equipment controller.
本文主要通过FPGA器件，利用HDL硬件描述语言，初步完成了USB设备控制器的设计和实现。
11
For the realization of this architecture, we propose a software simulation by VHDL.
对于该架构的实现，本文提出了VHDL层面的软件模拟。
12
CPLD using the top of the control procedures and the underlying graphics input VHDL mixed language design of the modular design method.
CPLD的控制程序采用顶层图形输入法和底层VHDL语言模块设计的混合设计方法完成。
13
I graduated from the core task is to design: FPGA to create a VHDL-based language of the digital voltmeter.
我的毕业设计的核心任务是：采用FPGA来制作一个基于VHDL语言编写的数字电压表。
14
This paper is arranged around the apply of VHDL in digital system design.
本文正是围绕硬件描述语言在数字硬件系统设计中的应用来展开的。
15
And its attraction and currency act well. It refers to VHDL, hardware design, C and compunication.
论文主要涉及VHDL语言设计、硬件电路设计、C语言程序设计和计算机通信等。
16
Vhdl design and then synchronize with asynchronous clear and clock enable control counter decimal addition and subtraction.
再用vhdl设计含异步清零和同步时钟使能的十进制加减可控计数器。
17
Adder can be used to represent various values, such as: BCD, plus three yards, the major operator for a binary adder.
加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。加法器可以用组合逻辑电路实现也可以用VHDL语言实现。
18
But the VHDL language simplifies the entire system significantly and improves the overall functions and reliability.
基于VHDL语言，将使整个系统大大简化，提高整体的性能和可靠性。
19
Firstly, we improve the arithmetic of FIR filter. Then we design each module of the audio processing chip by VHDL.
首先对FIR滤波器的算法进行了改良，然后采用VHDL语言对音频处理芯片的每个模块分别设计。
20
A model of dynamic load balancing was established after analyzed the particularity of parallel VHDL simulation.
对并行VHDL模拟的特殊性进行分析后，建立了一个并行VHDL模拟的动态负载平衡模型。
21
In the design, the median filter is chose to process images. The key algorithm is achieved through the VHDL.
在设计时，选用中值滤波算法对图像进行处理，核心算法的实现则通过VHDL语言实现的。
22
At last I use VHDL to realize the coordinate transform in the gauge automatic measurement system and achieve simulation.
最后利用VHDL语言编程实现轨距检测中的坐标变换，并仿真。
23
VHDL? Very high speed integrated circuit Hardware Description Language?
甚高速集成电路硬件描述语言？。
24
use C language and VHDL LCD controller using examples of the use of modules : SCM modules, LCD display modules.
使用C语言与VHDL实现液晶显示控制器示例使用说明使用模块有：单片机模块、液晶显示模块。
25
VHDL? Visual Hardware Description Language?
视觉硬件描述语言？。
26
in order to carry through AC sampling and multi-cycle synchronous frequency measurement, the language of C196 and VHDL have been introduced.
下位机采用C196和VHDL语言实现交流采样电压电流及多周期同步测频。
27
While the designing methods of VHDL have the peculiarities of non-depending of parts, easily being transplanted and accelerating designing.
而采用VHDL进行设计输入的设计方法有着不依赖器件，移植容易，能加快设计的特点。
28
This paper designs and implements a Sprinkling irrigation system of temperature controlled timing with VHDL language under the MAX+PLUS II.
文章在MAX+PLUSII开发环境下采用VHDL语言，设计并实现了温控定时喷灌系统，讨论了系统的三个组成模块的设计和VHDL实现。
29
The CPLD module has been developed to implement system logic control and sampled data storage by VHDL.
采用硬件描述语言（VHDL）对CPLD进行开发，实现了系统的逻辑控制和采样数据的存储。
30
Nowadays, FPGA and VHDL are two important tools in embedded system design.
FPGA和VHDL是当今嵌入式系统设计的两个重要工具。