vhdl

可以的啊，实现起来应该相当简单的

Formal Definition: An alternate name for an existing named entity. Complete description: Language Reference Manual §4.3.3. Simplified Syntax: alias alias_name : alias_type is object_name; Description: The alias declares an alternative name for any existing object: signal, variable, constant or file. It can also be used for "non-objects": virtually everything, which was previously declared, except for labels, loop parameters, and generate parameters. Alias does not define a new object. It is just a specific name assigned to some existing object. Aliases are prevalently used to assign specific names to slices of vectors in order to improve readability of the specification (see example 1). When an alias denotes a slice of an object and no subtype indication is given then the subtype of the object is viewed as if it was of the subtype specified by the slice. If the alias refers to some other object than a slice and no subtype indication is supported then the object is viewed in the same way as it was declared. When a subtype indication is supported then the object is viewed as if it were of the subtype specified. In case of arrays, the subtype indication can be of opposite direction than the original object (example 2). Subtype indication is allowed only for object alias declarations. A reference to an alias is implicitly a reference to the object denoted by the alias (example 3). If an alias denotes a subprogram (including an operator) or enumeration literal then a signature (matching the parameter and result type) is required (example 4). See signature for details. Examples: Example 1 signal Instruction : Bit_Vector(15 downto 0); alias OpCode : Bit_Vector(3 downto 0) is Instruction(15 downto 12); alias Source : Bit_Vector(1 downto 0) is Instruction(11 downto 10); alias Destin : Bit_Vector(1 downto 0) is Instruction(9 downto 8); alias ImmDat : Bit_Vector(7 downto 0) is Instruction(7 downto 0); The four aliases in the example above denote four elements of an instruction: operation code, source code, destination code and immediate data supported for some operations. Note that in all declarations the number of bits in the subtype indication and the subtype of the original object match. Example 2 signal DataBus : Bit_Vector(31 downto 0); alias FirstNibble : Bit_Vector(0 to 3) is DataBus(31 downto 28); DataBus and FirstNibble have opposite directions. A reference to FirstNibble(0 to 1) is equivalent to a reference to DataBus(31 downto 30). Example 3 signal Instruction : Bit_Vector(15 downto 0); alias OpCode : Bit_Vector(3 downto 0) is Instruction(15 downto 12); . . . if Opcode = "0101" -- equivalent to if Instruction(15 downto 12) = "0101" then . . . Both conditions are exactly the same, but the one where alias is used is more readable. Important notes: ˇ VHDL Language Reference Manual uses the name "entity" to denote a language unit, i.e. object, parameter etc. It is completely different idea than a design entity. ˇ Many synthesis tools do not support aliases.

端口声明语法错误，bclk : in std_logic; -- :左右要有空格

思路：8421码：高-->低d,c,b,a1,0,0,1--91,0,0,0---80,0,1,1---3所以，>=8，就是d=1；3<=，就是d&c=0，则f=d+（d*c）非；其余的，希望你能够自己去完成

假设a和b是两个本位操作数，c_in是低位向本位的进位，sum是本位和，c_out是本位向高位的进位，都是std_logic类型的；input是进程体内声明的std_logic_vector类型的变量。只列出行为描述部分的代码，你需要用进程语句将其包装成并行语句：input := c_in & b & a;case input is when "000" => sum <= "0"; c_out <= "0"; when "001"|"010"|"100" => sum <= "1"; c_out <= "0"; when "011"|"110"|"101" => sum <= "0"; c_out <= "1"; when "111" => sum <= "1"; c_out <= "1"; when others => sum <= "-"; c_out <= "-";end case;

我不知道，我不知道，我不知道

分配引脚？你要是有开发板的话，都应该有pin assignment file吧，有的话，直接载入，然后把VHDL里的signal 名字改成你需要的信号名（pin assignment file里的）如果没有，自己分配时，要看你的板子上的引脚都怎么与FPGA芯片链接的，然后查pin planner 图，找到正确的pin，比如7 seg LED 一般会连到FPGA的某几个pin上，至于clk signal，FPGA内部有专门的PLL clock source，你把你的clk信号名assign给clock source pin 即可。

这要看你用的是什么芯片了，每个芯片接的都不一样，但芯片上有提示，如果你用的是Quartus2的话，在PINPlanner界面，能绑定时钟的管脚上会有一个上升沿或者下降沿的符号，或者把鼠标放在一个引脚上，它会有提示说是IO口还是什么，如果是DedicatedClock,clk1/lvd或类似含clk的提示，那么这个就可以讲时钟信号绑在该管脚上。如果你用是MaxPlus2的话在FloorplanEditor界面的管脚上就直接有提示，GlobalCLK，你就可以把管脚绑上了。

这要看你用的是什么芯片了，每个芯片接的都不一样，但芯片上有提示，如果你用的是Quartus2的话，在PINPlanner界面，能绑定时钟的管脚上会有一个上升沿或者下降沿的符号，或者把鼠标放在一个引脚上，它会有提示说是IO口还是什么，如果是DedicatedClock,clk1/lvd或类似含clk的提示，那么这个就可以讲时钟信号绑在该管脚上。如果你用是MaxPlus2的话在FloorplanEditor界面的管脚上就直接有提示，GlobalCLK，你就可以把管脚绑上了。

这是实验课上做过的序列检测器的代码，参考一下吧，序列检测器有6个状态s0,s1,s2,s3,s4,s5检测的序列是010111。LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY exp_detect3 IS PORT ( clock : IN STD_LOGIC; reset : IN STD_LOGIC; din : IN STD_LOGIC; z : OUT STD_LOGIC );END exp_detect3;ARCHITECTURE bhv OF exp_detect3 IS TYPE type_state IS (s0,s1,s2,s3,s4,s5); SIGNAL state : type_state; --SIGNAL reg_fstate : type_fstate;BEGIN -- PROCESS (clock,reset,reg_fstate) process(clock,reset) BEGIN IF reset="1" THEN state <= s0; ELSIF (clock="1" AND clock"event) THEN case state is WHEN s0 => IF din = "0" THEN state <= s1; else state <= s0; END IF; --z <= "0"; WHEN s1 => IF din = "1" THEN state <= s2; else state <= s1; END IF; --z <= "0"; WHEN s2 => IF din = "0" THEN state <= s3; else state <= s0; END IF; -- z <= "0"; WHEN s3 => IF din = "1" THEN state <= s4; else state <= s1; END IF; --z <= "0"; WHEN s4 => IF din = "1" THEN state <= s5; else state <= s3; END IF; -- z <= "0"; WHEN s5 => IF din = "1" THEN state <= s0; else state <= s1; END IF; --z <= "0"; end case; END IF;end process;process(state,din) begin case state is when s5=> if din="1"then z<="1"; else z<="0"; end if; when others=> z<="0"; end case; end process; END bhv;